Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs

The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most them depend on batteries to operate. target this work is decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding over binary circuits (2) carbon nanotube field-effect transistors (CNFET) show better performance than CMOS. This proposes ternary combinational 32 nm CNFET: Ternary Half Adder (THA) with 36 Multiplier (TMUL) 23 transistors. To reduce utilizing the unary operator system employing two voltage supplies ( $V_{dd}$ /2). result extensive HSPICE simulations PVT (Process, Voltage, Temperatures) variations Noise Immunity Curve (NIC) improvements proposed designs up 25% in count 98% reductions. Further, increasing robustness process noise tolerance compared recent similar designs.